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32 megabit flash eeprom dp5z2mw16pn3 preliminary description: the dp5z2mw16pn3 ??slcc?? devices are a revolutionary new memory subsystem using dense-pac microsystems? ceramic stackable leadless chip carriers (slcc). available unleaded, straight leaded, ??j?? leaded, gullwing leaded packages, or mounted on a 50-pin pga co-fired ceramic substrate. the device packs 64-megabits of flash eeprom in an area as small as 0.463 in 2 , while maintaining a total height as low as 0.171 inches. the dp5z2mw16pn3 contains two individual 1 meg x 16 flash eeprom memory devices. each slcc is hermetically sealed making the module suitable for commercial, industrial and military applications. by using slccs, the ??stack?? family of modules offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. features: organization: 2meg x 16 fast access times: 120, 150, 200ns (max.) single 5.0 volt high-density symmetrically blocked architecture - sixteen 64 k word blocks per device extended cycling capability - 100k write/erase cycles automated erase and program cycles - command user interface - status register sram-compatible write interface hardware data protection feature - erase / write lockout during power transitions packages available: dp5z2mw16py3 48 - pin slcc dp5z2mw16pi3 48 - pin straight leaded slcc dp5z2mw16ph3 48 - pin gullwing leaded slcc dp5z2mw16pj3 48 - pin ??j?? leaded slcc dp5z2mw16pa3 50 - pin pga dense-slcc 2mx16, 120 - 200ns, stack/pga 30a161-22 a this document contains information on a product presently under development at dense-pac microsystems, inc. dense-pac reserves the right to change products or specifications herein without prior notice. slcc stack straight leaded stack ??j?? leaded stack gullwing leaded stack dense-stack 30a161-22 rev. b 1
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary pin-out diagram 48 - pin leadless slcc 48 - pin straight leaded slcc 48 - pin ??j?? leaded slcc 48 - pin gullwing leaded slcc 50 - pin pga dense-stack functional block diagram 30a161-22 rev. b 2
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary bus operation flash memory reads, erases and writes in-system via the local cpu. all bus cycles to or from the fl ash memory conform to standard microprocessor bus cycles. table 1: bus operation mode ce oe we a0 a1 a9 i/o0-i/o15 read 1 v il v il v ih x x x d out output disable 1 v il v ih v ih x x x high-z standby 1 v ih x x x x x high-z deep power-down 1 x x x x x x high-z manufacturer identifier 1, 3 v il v il v ih v il v il v id 00c2h device identifier 3 v il v il v ih v ih v il v id 00f1h write 1, 2 v il v ih v il x x x d in notes: 1. x can be v il or v ih for address or control pins. 2. command for deferent erase operations, data program operations or selector protect operations can on ly be successfully completed through proper command sequence. 3. v id = 11.5v - 12.5v. write operation commands are written to the command interface register (cir) using standard microprocessor write timing. the cir serves as the interface between the microprocessor and the internal chip operation. the cir can decipher read array, read silicon id, erase and program command. in the event of a read command, the cir simply points the read path at either the array or the silicon id, depending on the specific read command given. for a program or erase cycle, the cir informs the write state machine that a program or erase has been requested. during a program cycle, the write state machine control the program sequences and the cir will only respond to status reads. during a sector/chip erase cycle, the cir will respond to status reads and erase suspend. after the writhe state machine has completed its task, it will allow the cir to respond to its full command set. the cir stays at read status register mode until the microprocessor issues another valid command sequence. device operations are selected by writing commands into the cir. table 3 below defines 16 megabit flash family command. pin names a0 - a19 address inputs: for memory address. addresses are internally latched during a write cycle. i/o0 - i/o15 data input/output: input data and command during command data interface register (cir) write cycles. outputs array, status and identifier data in the appropriate read mode. floated when the c hip is de-selected or the outputs are disabled. ce chip enable input: activate the device?s control logic, input buffers, decoders and sense amplifiers . with ce high, the device is de-selected and power consumption reduces to standby level upon completion of a ny current program or erase operation. ce must be low to select the device. device selection occurs with the falling edge of ce . the rising edge of ce disables the device. we write enable: controls writes to the command interface register (cir). we is active low. oe output enable: gates the device?s data through the output buffers during a read cycle. oe is active low. v dd device power supply (+5.0 volts 10%) v ss ground n.c. no connect 30a161-22 rev. b 3
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary device operation silicon id read the silicon id read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate the mode, the programming equipment must force v id (11.5v ~ 12.5v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all addresses are don?t cares except a0 and a1. the manufacturer and device codes may also be read via the command register, for instance when the device is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in table 2. to terminate the operation, it is necessary to write the read/reset command sequence into the cir. read reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled fro reads until the cir contents are altered by a valid command sequence. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. table 2: command definition command sequence bus cycles req?d first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle address data address data address data address data address data address data read/reset 4 5555h aah 2aaah 55h 5555h f0h ra rd - - - - silicon id read 4 5555h aah 2aaah 55h 5555h 90h 00h/01h c2h/f1h - - - - page/byte program 4 5555h aah 2aaah 55h 5555h a0h pa pd - - - - chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h erase suspend 3 5555h aah 2aaah 55h 5555h b0h - - - - - - erase resume 3 5555h aah 2aaah 55h 5555h d0h - - - - - - read status register 4 5555h aah 2aaah 55h 5555h 70h x srd - - - - clear status register 3 5555h aah 2aaah 55h 5555h 50h - - - - - - sleep 3 5555h aah 2aaah 55h 5555h c0h - - - - - - abort 3 5555h aah 2aaah 55h 5555h e0h - - - - - - notes: ? address bit a15 - a19 = x = don?t care for all address commands except for programming address (pa) and sector address (sa). 5555h and 2aaah address command codes stand for hex number starting from a0 to a14. ? bus operations are defined in table 2. ? ra = address of the memory location to be read. pa = address of the memory to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a16 - a19 will be uniquely select any s ector. ? rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we . srd = data read from status register. table 3: silicon id code type a19 a18 a17 a16 a1 a0 code (hex) i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 manufacturer?s code x x x x v il v il 00c2h 1 1 0 0 0 0 1 0 device code x x x x v il v ih 00fih 1 1 1 1 0 0 0 1 30a161-22 rev. b 4
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary page program to initiate page program mode, a three-cycle command sequence is required. there are two ?unlock? write cycles. these are followed by writing the page program command - a0h. after three-cycle command sequence is given, a word load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . maximum of 64 words of data may be loaded into each page by the same procedures as outlined in the page program section below. word load word loads are used to enter the 64 words of a page to be programmed. a word load is performed by applying a low pulse on the we or ce input ce or we low respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . program any page to be programmed should have the page in the erase state first, i.e. performing sector erase is suggested before page programming can be performed. the device is programmed on a page basis. if a word of data within a page is to be changed, data for the entire page can be loaded into the device. any word that is not loaded during the programming of its page will be still in the erase state (i.e. ffh). once the words of a page are loaded into the device, they are simultaneously programmed during the internal programming period. after the first data word has been loaded into the device, successive words are entered in the same manner. each new word to be programmed must have its high to low transition on we (or ce ) within 30 m s of the low to high transition of we (or ce ) of the preceding word. a6 to a19 specify the page address, i.e. the device is page-aligned on 64 words boundary the page address must be valid during each high to low transition of we or ce . a0 to a5 specify the word address within the page. the word may be loaded in any order; sequential loading is not required. if a high to low transition of ce or we is not detected within 100 m s of the last low to high transition, the load period will end and the internal programming period will start. the auto page program terminates when status on i/o7 is ?1" at which time the device stays at read status register mode until the cir contents are altered by a valid command sequence. (refer to table 2 & 5 and figure 1, 6 & 7) chip erase chip erase is a six-bus cycle operation. there are two ?unlock? write cycles. these are followed by writing the ?set-up? command - 80h. two more ?unlock? write cycles are then followed by the chip erase command - 10h. chip erase does not require the user to program the device prior to erase. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the status on i/o7 is ?1" at which time the device stays at read status register mode until the cir contents are altered by a valid command sequence. (refer to tables 2 & 5 and figures 2, 6 & 8) table 4: sector address* a19 a18 a17 a16 address range [a0-a15] sa0 0 0 0 0 00000h?0ffffh sa1 0 0 0 1 10000h?1ffffh sa2 0 0 1 0 20000h?2ffffh sa3 0 0 1 1 30000h?3ffffh sa4 0 1 0 0 40000h?4ffffh ... .... ... ... ................ sa15 1 1 1 1 f0000h?fffffh * per 1 meg x 16 device. sector erase sector erase is a six-bus cycle operation. there are two ?unlock? write cycles. these are followed by writing the set-up command - 80h. two more ?unlock? write cycles are then followed by the sector erase command - 30h. the sector address is latched on the falling edge of we , while the command (data) is latched on the rising edge of we . sector erase does not require the user to program the device prior to erase. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins on the rising edge of the last we pulse in the command sequence and terminates when the status on i/o7 is ?1" at which time the device stays at read status register mode. the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence. (refer to tables 2, & 5 and figures 3, 4, 6 & 8) erase suspend this command only has meaning while the wsm is executing sector or chip erase operations, and therefore will only be responded to during sector or chip erase operation. after this command has been executed, the cir will initiate the wsm to suspend erase operations, and then return to read status register mode. the wsm will set the i/o6 bit to a ?1". once the wsm has reached the suspend state, the wsm will set i/o7 bit to a ?1". at this time, wsm allows cir to respond to the read array, read status register, abort and erase resume commands only. in this mode, the cir will not respond to any other commands. the wsm will continue to run, idling in the suspend state, regardless of the state of all input control pins. erase resume this command will cause the cir to clear the suspend state and set the i/o6 to a ?0", but only in an erase suspend command was previously used. erase resume will not have any effect in all other conditions. read status register command the module contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status command to the cir. after writing this command, all subsequent read operations output data from the status register, until another valid command is written to the cir. a read array command must be written to the cir to return to the read array mode. 30a161-22 rev. b 5
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary the status register bits are output on i/o2 - i/o7 (table 5), i/o0-i/o1 and i/o8-i/o15 is set to 0h. it should be noted that the status register are latched on the falling edge of oe or ce whichever occurs last in the read cycle. this prevents possible bus errors which might occur if the contents of the status register change while reading the status register. ce or oe must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. the status register is the interface between the microprocessor and the write state machine (wsm). when the wsm is active, this register will indicate the status of the wsm, and will also hold the bits indicating whether or not the wsm was successful in performing the desired operation. the wsm sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. if erase fail or program fail status bit is detected, the status register is not cleared until the clear status register command is written. the device automatically outputs status register data when read after chip erase, sector erase, page program or read status command write cycle. the default state of the status register after power-up and return from deep power-down mode is (i/o7, i/o6, i/o5, i/o4) = 1000b. i/o3 = 0 or 1 depends on sector-protect status, can not be changed by clear status register command or write state machine. i/o2 = 0 or 1 depends on sleep status, during sleep mode or abort mode i/o2 is set to ?1"; i/o2 is reset to ?0" by read array command. clear status register the erase fail status bit (i/o5) and program fail status bit (i/o4) are set by the write state machine, and can only be reset by the system software. these bits can indicate various failure conditions (see table 5). by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in sequence). the status register may then be read to determine if an error occurred during that programming or erasing series. this adds flexibility to the way the device may be programmed or erased. additionally, once the program (erase) fail bit happens , the program (erase) operation can not be performed further. the program (erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. to clear the status register, the clear status register command is written to the cir. then, any other command may be issued to the cir. note again that before a read cycle can be initiated, a read command must be written to the cir to specify whether the read data is to come from the array, status register or silicon id. sleep mode the device features two software controlled low-power modes: sleep and abort modes. sleep mode is allowable during any current operations except that once suspend command is issued, sleep command is ignored. abort mode is executed only during page programming and chip/sector erase mode. to activate sleep mode, a three-bus cycle operation is required. c0h command (refer to table 2) puts the device in the sleep mode. once in the sleep mode and cmos input level applied, the power of the device is reduced to deep power-down current levels. the only threshold condition, input leakage, and output leakage. the sleep command allows the device to complete current operations before going into sleep mode. once current operation is done, device stays at read status register mode. the status table 5: status register status i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 in progress program a, b, f 0 0 0 0 0/1 0/1 erase a, c, f 0 0 0 0 0/1 0/1 suspend (not complete) a, d, f 0 1 0 0 0/1 0/1 suspend (complete) a, d, f 1 1 0 0 0/1 0/1 complete program a, b, f 1 0 0 0 0/1 0/1 erase a, c, f 1 0 0 0 0/1 0/1 fail program a, e, f 1 0 0 1 0/1 0/1 erase a, e, f 1 0 1 0 0/1 0/1 after clearing status register f 1 0 0 0 0/1 note ?g? notes: a. i/o7: write state machine status 1 = ready, 0 = busy i/o6: erase suspend status 1 = suspend, 0 = no suspend i/o5: erase fail status 1 = fail in erase, 0 = successful erase i/o4: program fail status 1 = fail in program, 0 = successful program i/o3: sector-protect status (not used) i/o2: sleep status 1 = device in sleep status, 0 = device not in sleep status i/o1 - i/o0 = reserved for further enhancements. these bits are reserved for future use; mask them out when polling the status register. b. program status is for the status during page programming or sector unprotect mode. c. erase status is for the status during sector/chip erase or sector protection mode. d. suspend status is for both sector and chip erase mode. e. fail status bit (i/o4 or i/o5) is provided during page program or sector/chip erase modes respectively. f. i/o2 = 0 or 1 depends on whether device is in the sleep mode or not. g. once in the sleep mode, i/o2 is set to ?1", and is reset by read array command only. 30a161-22 rev. b 6
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary registers are not reset during sleep command. program or erase fail bit may have been set if during program/erase mode the device retry exceeds maximum count. during sleep mode, the status registers, silicon id codes remain valid and can still be read. the device sleep status bit - i/o2 will indicate that the device in the sleep mode. write and read array command wakes up the device out of sleep mode, i/o2 is reset to ?0" and device returns to standby current level. abort mode to activate abort mode, a three-bus cycle operation is required. the e0h command (refer to table 3) only stops page program or sector/chip erase operations currently in progress and puts the device in sleep mode. but unlike the sleep command, the program or erase operation will not be completed. since the data in some page/sectors is no longer valid due to an incomplete program or erase operation, the program fail (i/o4) or erase fail (i/o5) bit will be set. after the abort command is executed and with cmos input levels applied, the device current is reduced to the same level as in deep power-down or sleep modes. device stays at read register mode. during abort mode, the status register, silicon id codes remain valid and can still be read. the device sleep status bit - i/o2 will indicate that the device in the sleep mode. data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exit during power transitions. during power-up the device automatically resets the internal state machine in the read array mode. also, with its control register architecture, alterations of the memory contents only occurs after successful completion of specific multi-bus cycles command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v dd power-up and power-down transitions or system noise. low v dd write inhibit to avoid initiation of a write cycle during v dd power-up and power-down, a write cycle is locked out for v dd less than v okl (=3.2v, typically 3.5v). if v dd < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v dd level is greater than v lko . it is logically correct to prevent unintentional write when v dd is above v lko . write pulse ?glitch? protection noise pulses of less than 10ns (typical) on ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. erase and programming performance parameter limits units min. typ. max. chip/sector erase time 150 2000 ms page programming time 3 60 ms chip program time 48 150 sec erase/program cycles 10,000 cycles byte program time 24 m s latch up characteristics parameter min. amx. units input voltage with respect to v ss on all pins except i/o pins -1.0 13.5 v input voltage with respect to v ss on all i/o pins -1.0 v dd +1.0 v current -100 +100 ma includes all pins except v dd . test conditions: v dd = 5.0v, one pin at a time 30a161-22 rev. b 7
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary recommended operating range 1 symbol characteristic min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v il input low voltage -0.5 2 0.8 v v ih input high voltage 2.0 v dd +0.5 v t a operating temperature c 0 +25 +70 c i -40 +25 +85 m/b -55 +25 +125 v id a9 i.d. input/output 11.5 12.5 v absolute maximum ratings 5 symbol parameter value unit t stc storage temperature -65 to +125 c t bias temperature under bias -55 to +125 c t op operating temperature -55 to +125 c i out output short circuit current 100 4 ma v i/o input/output voltage 1 -0.5 to +7.0 2 v v dd supply voltage 1 -0.5 to +7.0 3 v capacitance 5 : t a = 25 c, f = 1.0mhz symbol parameter max. unit condition c adr address input 30 pf v in 2 = 0v c ce chip enable 20 c we write enable 30 c oe output enable 30 c i/o data input/output 35 dc output characteristics symbol parameter condition min. max. unit v oh high voltage i oh = -400 m a 2.4 v v ol low voltage i ol =2.1ma 0.45 v dc operating characteristics: over operating ranges symbol characteristics test conditions limits unit min. typ. max. i il input load current 6 v dd = v dd max., v in =v dd or v ss -20 +20 m a i ol output leakage current 6 v dd = v dd max., v in =v dd or v ss -20 +20 m a i sb1 v dd standby current (cmos) 6 v dd = v dd max., ce = v dd 0.2v 100 400 m a i sb2 v dd standby current (ttl) 6 v dd = v dd max., ce = v ih 4 12 ma i cc1 v dd read current v dd = v dd max., ce = v il , inputs = v il or v ih , f = 10mhz, i out = 0ma 55 100 ma i cc2 v dd read current 6 v dd = v dd max., ce = v il , inputs = v il or v ih , f = 5mhz, i out = 0ma 35 60 ma i cc3 v dd erase suspend current 6, 8 block erase in suspend, ce = v ih 10 35 ma i cc4 v dd program current 6 program in progress 35 80 ma i cc5 v dd erase current 6 erase in progress 35 80 ma v il input low voltage 9 -3.0 0.8 v v ih input high voltage 2.4 v dd +0.3 v v ol output low voltage i ol = 2.1ma 0.45 v v oh output high voltage i oh = -400ma 2.4 v 30a161-22 rev. b 8
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary figure 1: automatic page program flow chart note: sr = status register 30a161-22 rev. b 9
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary figure 2: automatic chip erase flow chart 30a161-22 rev. b 10
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary figure 3: automatic sector erase flow chart 30a161-22 rev. b 11
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary figure 4: erase suspend/erase resume flow chart 30a161-22 rev. b 12
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary output load load c l parameters measured 1 100 pf except t df , t lz and t olz 2 30pf t df , t lz and t olz ac test conditions input pulse levels 0.45v to 2.4v input pulse rise and fall times 10ns input and output timing reference levels 0.8v, 2.0v ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 120ns 150ns 200ns unit min. max. min. max. min. max. 1 t acc address to output delay 120 120 150 ns 2 t ce chip enable output delay 120 120 150 ns 3 t oe output enable output delay 60 70 80 ns 4 t df output enable to output delay 0 55 0 55 0 70 ns 5 t oh address to output hold 0 0 0 ns ac input output reference waveform ac test inputs are driven at v oh (2.4 v ttl ) for logic ?1?? and v ol (0.45 v ttl ) for a logic ??0??. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to ()%) < 10ns. output load +5v 1.8k w diodes = in3064 or equivalent c l * 6.2k w * including probe and jig capacitance. device under test 30a161-22 rev. b 13
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary figure 5: read cycle address ce oe we data i/o v dd ac operating conditions and characteristics - write/erase/program cycle: over operating ranges no. symbol parameter 120ns 150ns 200ns unit min. max. min. max. min. max. 6 t wc write cycle time 120 150 200 ns 7 t as address setup time 0 0 0 ns 8 t ah address hold time 50 60 70 ns 9 t ds data setup time 50 60 70 ns 10 t dh data hold time 10 10 10 ns 11 t oes output enable setup time 0 0 0 ns 12 t ces chip enable setup time 0 0 0 ns 13 t ghwl read recovery time before write 0 0 0 ns 14 t cs chip enable setup time 0 0 0 ns 15 t ch chip enable hold hold time 0 0 0 ns 16 t wp write pulse width 50 60 70 ns 17 t wph write pulse width high 50 50 50 ns 18 t balc byte address load cycle 0.3 30 0.3 30 0.3 30 m s 19 t bal byte address load time 100 100 100 m s 20 t sra status register access time 120 150 200 ns 21 t cesr chip enable setup before sr read 100 100 100 ns 22 t vcs v dd setup time 2 2 2 m s 30a161-22 rev. b 14
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary figure 6: write cycle ce oe we address data i/o v dd figure 7: automatic page program cycle 10 a0 - a5 a6 - a14 a15 - a19 ce we oe data i/o 30a161-22 rev. b 15
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary figure 8: automatic sector/chip erase cycle note: * = don?t care, sa = sector address, refer to page 5 for detail page program operation. a0 - a14 a15 a16 - a19 ce we oe data i/o ac operating conditions and characteristics write/erase/program operation alternate ce controlled writes: over operating ranges no. symbol parameter 120ns 150ns 200ns unit min. max. min. max. min. max. 23 t wc write cycle time 120 150 200 ns 24 t as address setup time 0 0 0 ns 25 t ah address hold time 50 60 70 ns 26 t ds data setup time 50 60 70 ns 27 t dh data hold time 10 10 10 ns 28 t oes output enable setup time 0 0 0 ns 29 t ces chip enable setup time 0 0 0 ns 30 t ghwl read recovery time before write 0 0 0 ns 31 t ws write enable setup 0 0 0 ns 32 t wh write enable hold time 0 0 0 ns 33 t cp chip enable pulse width 50 60 70 ns 34 t cph chip enable pulse width high 50 50 50 ns 35 t vcs v dd setup time 2 2 2 m s 30a161-22 rev. b 16
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary figure 9: command write timing (alternate ce controlled) figure 10: automatic page program timing cycle 10 a0 - a5 a6 - a14 a15-a19 we ce oe data i/o we oe ce address data i/o v dd 30a161-22 rev. b 17
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary notes: 1. all voltages are with respect to v ss . 2. -2.0v min. for pulse width less than 20ns (v il min. = -0.5v at dc level). 3. maximum dc voltage on v pp or a9 may over shoot to +14.0v for periods less than 20ns. 4. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex tended periods may affect reliability. 5. this parameter is guaranteed and not 100% tested. 6. all currents are in rms unless otherwise noted. typical values at v dd = 5.0v, t = 25 c. these currents are valid for all product versions (package and speeds.). 7. i cc3 is specified with the device de-selected. if the device is read while in erase suspend mode, curre nt draw is the sum of i cc3 and i cc1 /i cc2 . 8. v il min. = -1.0v for pulse width 50ns. 9. v il min. = -2.0v for pulse width 20ns. 10. refer to page 5 for detail page program operation. waveform key data valid transition from transition from data undefined high to low low to high or don?t care 30a161-22 rev. b 18
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary (48 - pin leadless slcc) mechanical drawing (48 - pin straight leaded slcc) mechanical drawing 30a161-22 rev. b 19
dp5z2mw16pn3 dense-pac microsystems, inc. preliminary (48 - pin ??j?? leaded slcc) mechanical drawing (48 - pin gullwing leaded slcc) mechanical drawing 30a161-22 rev. b 20
dense-pac microsystems, inc. dp5z2mw16pn3 preliminary dense-pac microsystems, inc. 7321 lincoln way, garden grove, california 92841-1431 (714) 898-0007 (800) 642-4477 fax: (714) 897-1772 http://www.dense-pac.com ordering information (50 - pin pga) mechanical drawing 30a161-22 rev. b 21

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